Hybrid-Timing FIFOs to Use on Networks-on-Chip in GALS Architectures

This paper presents three high-throughput low-latency FIFOs that can be used as efficient and reliable interfaces between different domains in hybrid-timing systems. These three hardware components have been designed to be used in a Globally Asynchronous Locally Synchronous clusterized Multi-Processor System-on-Chip communicating by a Multi-Synchronous or by a fully Asynchronous Network-on-Chip. The proposed architectures are rather generic and allow the system designer to make various trade-off between latency and robustness, depending on selected synchronizer. These FIFOs have been physically implemented with portable ALLIANCE CMOS standard cell library and the architectures have been evaluated by SPICE simulation for a 90nm CMOS fabrication process.